1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor and an apparatus using the method, and more particularly, to a method of arranging assist features within mask patterns and an apparatus using the method.
2. Description of the Related Art
One of the goals in integrated circuit fabrication is to faithfully reproduce the original circuit design on a semiconductor wafer via a mask using as much area of the semiconductor wafer as possible. Another goal is to optimize exposure and improve image intensity on the semiconductor wafer. Yet another goal is to increase depth of focus (DOF) and exposure latitude (EL). However, the microscopic size of main features makes it difficult for light to pass through holes or lines on the mask. Consequently, the DOF and the EL are reduced.
Conventional methods suggested in order to solve this problem include a method of arranging assist features on a mask such that light intensity on a feature to be generated can be increased (which, in turn, will increase DOF and EL). Currently, the assist features are arranged by an engineer through trial and error in accordance with the engineer's ability and skill such that a large amount of time is required. Furthermore, the assist features cannot be arranged on a broad area of the mask in consideration of the overall pattern of the mask. Finally, if the mask has various patterns thereon, stable generation of the assist features cannot be guaranteed.
Therefore, a new method of determining optimal positions of the assist features is required.